1. Field of the Invention
The invention relates to a memory apparatus, and more particularly, to a non-volatile memory apparatus and an operating method thereof.
2. Description of Related Art
Generally, during operation of a SSD (solid state disk/drive) or a memory disk, a mapping table is required for recording a mapping relation (conversion relation) between a logical address and a physical address. The logical address may include a logical block address (LBA) and/or a logical page address, and the physical address may include a physical block address (PBA) and/or a physical page address. A host usually accesses data stored in the SSD or the memory disk based on a variety of modes including Page Mapping, Block Mapping, Replacement Block or Log Block. Although contents stored by the mapping table corresponding to different modes may be different from one another, when an access command is received by the SSD or the memory disk from the host, the SSD or the memory disk must convert the logical address of the access command into the physical address of a flash memory in the SSD or the memory disk according to the mapping table, and then execute the access command to a physical memory (a physical block or a physical page) pointed by the physical address obtained after the conversion.
During the process of constantly executing the access commands of the host, a corresponding relation between the logical address and the physical address may be changed correspondingly, and thus the content of the mapping table may also be constantly updated. The mapping table is usually stored in a DRAM (dynamic random access memory) in order to accelerate an access speed. When the SSD or the memory disk performs a power-off procedure, the mapping table is kept in the flash memory in the SSD or the memory disk to ensure that the content of the mapping table is not lost due to the power-off procedure. When the SSD or the memory disk is powered on, the SSD performs an initialization procedure. In the initialization procedure, the SSD or the memory disk may read the mapping table from the flash memory and writes the mapping table back to the DRAM.
In general, when one specific memory cell of the flash memory is read, a method for reading the flash memory may result in an undesirable change in bit data of other memory cells near the specific memory cell of the same block. This undesirable change is the so-called “data read disturbance”. With respect to one physical page of the flash memory, after performing a read operation to that physical page multiple times, a number of error bits in that physical page increases with increases in usage time (or increases in a read-count). Normally, the flash memory is configured with an ECC (Error Checking and Correcting) mechanism. When the number of error bits per unit bit (e.g., 1K Byte, or a number of bits in one physical page) in the data is less than one specific tolerable number, the ECC mechanism is able to correct the error bits so the flash memory may provide correct data to the host. When the number of error bits per unit bit in the data is greater than the specific tolerable number, the ECC mechanism is unable to correct the error bits. Excessive number of error bits which are uncorrectable by the ECC mechanism will result in data loss.